Multi-Core RC4 Decoder/Cracker
FPGA-based multi-core RC4 decoder design and implementation using Verilog with parallel processing architecture for efficient cryptanalysis.
2 min read
FPGA Verilog Cryptography Parallel Computing
Zihao Pu
PhD Student · King's College London
Department of Engineering, Faculty of Natural, Mathematical & Engineering Sciences
Processing-in-Memory · LLM Acceleration · Hardware-Software Co-Design
Research Interests
Processing-in-Memory (PIM)
Data-centric computing architectures that break the von Neumann memory bottleneck.
LLM Acceleration
Hardware acceleration for large language models, optimizing inference and training efficiency.
Hardware-Software Co-Design
Joint optimization of hardware and software for maximum AI workload performance.
Reconfigurable Computing
FPGA-based adaptive architectures for flexible computing requirements.
Research focus on hardware-software co-design to accelerate large-scale AI computations and overcome memory bottlenecks in LLMs and data-intensive applications. Member of SAIL Research Group.
Latest Posts
View All →Featured Publication
J. Gao, Z. Pu et al., "Smart Insole: Stand-Alone Soft 3-Axis Force Sensing Array in a Shoe," 2023 IEEE SENSORS, Vienna, Austria, 2023, pp. 1-4.
DOI: 10.1109/SENSORS56945.2023.10324863