About Me
PhD Student · King's College London
Biography
I am Zihao Pu, currently a PhD student at the Department of Engineering, King's College London, researching Processing-in-Memory (PIM) architectures and data-centric computing. My PhD thesis focuses on hardware-software co-design to accelerate large-scale AI computations, particularly addressing memory bottlenecks in Large Language Models (LLMs) and data-intensive applications.
I completed my Bachelor's degree in Electrical Engineering at the University of British Columbia (UBC) with Distinction, and my Master's degree in Integrated Circuit Design through a joint program between Nanyang Technological University (NTU) and Technical University of Munich (TUM), also graduating with Distinction.
Prior to my PhD, I interned at AMD implementing an RDMA-based SmartNIC architecture on FPGA and evaluating TSMC 7nm/3nm implementations for distributed ML training acceleration (resulting in a patent and Master's thesis). I also worked at A*STAR Institute of Microelectronics designing a high-speed SAR-ADC in TSMC 28nm for cryogenic quantum computing I/O systems, at Huawei Technologies on FPGA/CPLD glue logic for optical line terminal products, and at UBC's Molecular Mechatronics Lab on capacitive sensing systems (published at IEEE SENSORS 2023).
Research
PhD Thesis
"Processing-in-Memory Architectures for Data-Centric Computing: Hardware–Software Co-Design for Scalable AI Acceleration" (Provisional)
Supervisor: Dr Haiyu Mao · Co-supervisor: Dr Hak-Keung Lam
• Processing-in-Memory (PIM)
Data-centric computing architectures that break the von Neumann memory bottleneck.
• LLM Acceleration
Hardware acceleration for large language models, optimizing inference and training efficiency.
• Hardware-Software Co-Design
Joint optimization of hardware and software for maximum AI workload performance.
• Reconfigurable Computing
FPGA-based adaptive architectures for flexible computing requirements.
Education
MPhil/PhD in Engineering
King's College London
Department of Engineering, Faculty of Natural, Mathematical & Engineering Sciences
M.Sc. in Integrated Circuit Design (Distinction)
Nanyang Technological University & Technical University of Munich
Joint Degree Program · Sehr Gut Bestanden
B.A.Sc. in Electrical Engineering (Distinction)
University of British Columbia
Dean's Honour List 2020 & 2021 · Outstanding International Student Award (25,000 CAD)
Professional Experience
AMD
Jul. 2024 – Apr. 2025Research Intern · Singapore
Implemented an RDMA Engine into a SmartNIC using AMD FPGA and developed a heterogeneous computation system for distributed ML training acceleration. Evaluated the compute unit in TSMC 7nm and 3nm for PPA comparison. Resulted in a filed patent and Master's thesis.
A*STAR Institute of Microelectronics
Oct. 2023 – Oct. 2024Graduate Research Intern (Part-time) · Singapore
Designed quantum computer I/O systems in TSMC 28nm, focusing on a high-speed SAR-ADC (200 MSps, 8-bit) operating at both room temperature (300K) and cryogenic temperature (4K). Achieved post-simulation ENOB of 7.2. Completed physical design and GDS tape-out; silicon returned for testing.
Huawei Technologies
Jul. 2021 – Mar. 2022Hardware Engineer Intern · Dongguan, China
Led FPGA/CPLD glue logic development and testing for optical line terminal products. Designed verification-automation processes that reduced average verification time from 7 days to 1 day. Participated in full product lifecycle from design through release.
UBC Molecular Mechatronics Lab
Sept. – Dec. 2022Undergraduate Research Intern · Vancouver, Canada
Designed an insole sensor supporting multi-spot vector force sensing using capacitive sensors. Developed application software for sensor data readout and assisted with MCU PCB design. Published at IEEE SENSORS 2023.
Featured Publication
J. Gao, Z. Pu et al., "Smart Insole: Stand-Alone Soft 3-Axis Force Sensing Array in a Shoe," 2023 IEEE SENSORS, Vienna, Austria, 2023, pp. 1-4.
DOI: 10.1109/SENSORS56945.2023.10324863